This application relates to integrated circuit imaging arrays and to the pixel imaging cells which make up such arrays. The invention has particular application to imaging arrays implemented in CMOS technology and which afford high resolution, low power consumption and wide dynamic range.
Solid state imaging systems have been used for a number of years in various types of devices. While many of these systems utilize Charge-Coupled Devices (xe2x80x9cCCDxe2x80x9d) to build the underlying solid state image sensors, CCD-based sensors are limited by their process technology in that CMOS logic circuits cannot be incorporated onto the same substrate. Accordingly, less expensive imaging devices fabricated out of integrated circuits using standard CMOS processes have been developed. Such CMOS imaging devices typically include a light detecting element or sensor, such as a photodiode or photogate, the output of which is an analog signal with a magnitude approximately proportional to the amount of light perceived by the sensor. It is known to form such light detecting elements in a core array which is addressable by row and column. An analog-to-digital-converter (xe2x80x9cADCxe2x80x9d) may then be used to convert the analog signals to digital signals. Typically, the processing and storage capabilities utilized in the analog-to-digital conversion are located outside the sensing array, either on or off the chip. This has certain inherent disadvantages, particularly as regards scaling up the imaging array.
Efforts have heretofore been made to effect processing and/or storage within the imaging array at the pixel level. U.S. Pat. No. 6,362,482 discloses a detector based on counting charges or photons, which implements focal-plane pixel-parallel processing. However, in this device all processing is done in the analog domain, and there is no digital logic circuitry.
U.S. Pat. No. 6,271,785 discloses a CMOS imager which performs analog-to-digital conversion at the pixel cell level by comparing photodiode voltage to a ramp voltage. However, the ramp voltage is generated outside the array and the memory used to store the counter value is disposed outside the array. Kleinfelder et al., in a paper entitled xe2x80x9cA 10,000 Frames/s CMOS Digital Pixel Sensor with Pixel-Level Memoryxe2x80x9d, in Proceedings of the 2001-IEEE International Solid-State Circuits Conference, pages 88-89, San Francisco, Calif., February, 2001, describes a high-speed digital pixel sensor which incorporates single bit analog-to-digital conversion and embedded DRAM storage at the pixel level. The pixel incorporates a photosensor that integrates its current onto a capacitor to produce a voltage, which is compared at the pixel level with a ramped reference voltage signal which is generated external to the array. The device utilizes 3-transistor DRAM cells, which are not refreshable. The pixel is simply an on-off switch timer pixel and would not work with other types of pixels, such as an oscillator pixel.
There is disclosed in this application an integrated circuit imaging system which avoids the disadvantages of prior systems while affording additional structural and operating advantages.
An aspect is the provision of an imaging system which accommodates a very wide dynamic sensing range.
Another aspect is the provision of an imaging system which is characterized by very low power consumption.
Yet another aspect is the provision of an imaging system which has small unit cell size, permitting high-resolution image arrays within current CMOS process 5xc3x97 reticle limits.
Yet another aspect is the provision of a system of the type set forth, which affords linear scaling of power consumption with the number of pixels in the array.
A still further aspect is the provision of a system of the type set forth, which provides multi-bit analog-to-digital conversion by pixel-parallel processing.
In connection with the foregoing aspect, another aspect is the provision of a system of the type set forth, which provides arithmetic logic operations embedded within the pixel processor.
A still further aspect is the provision of a system of the type set forth, which provides multi-bit, refreshable, single-transistor, differential DRAM data storage per pixel.
Another aspect is the provision of a system of the type set forth, wherein sensor performance is independent of array size.
Certain ones of these and other aspects may be attained by providing a pixel processing and storage cell for use with a plurality of like cells in an integrated circuit imaging array, with each cell adapted to be coupled to a sensing unit having a binary output signal, the cell comprising a digital arithmetic logic processing circuit adapted to receive and process the output signal of an associated sensing unit to a processed multi-bit value, and a memory circuit coupled to the processing circuit and including a plurality of bit storage units for storing the processed value.